µC/OS-II Kernel

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μC/OS-II is a portable, ROMable, scalable, preemptive, real-time deterministic multitasking kernel for microprocessors, microcontrollers and DSPs. Offering unprecedented ease-of-use, μC/OS-II is delivered with complete 100% ANSI C source code and in-depth documentation. μC/OS-II runs on the largest number of processor architectures, with ports available for download from the Micrium Web site.

μC/OS-II manages up to 250 application tasks. μC/OS-II includes: semaphores; event flags; mutual-exclusion semaphores that eliminate unbounded priority inversions; message mailboxes and queues; task, time and timer management; and fixed sized memory block management.

μC/OS-II’s footprint can be scaled (between 5 Kbytes to 24 Kbytes) to only contain the features required for a specific application. The execution time for most services provided by μC/OS-II is both constant and deterministic; execution times do not depend on the number of tasks running in the application.

A validation suite provides all documentation necessary to support the use of μC/OS-II in safety-critical systems. Specifically, μC/OS-II is currently implemented in a wide array of high level of safety-critical devices, including:

• Those certified for Avionics DO-178B
• Medical FDA pre-market notification (510(k)) and pre-market approval (PMA) devices
• SIL3/SIL4 IEC for transportation and nuclear systems, 99% compliant with the Motor Industry Software Reliability Association (MISRA-C:1998) C Coding Standards

Applications

µC/OS-II is used in a wide variety of industries:

• Avionics
• Medical Equipment/Devices
• Data Communications Equipment
• White Goods (Appliances)
• Mobile Phones, PDAs, MIDs
• Industrial Controls
• Consumer Electronics
• Automotive
• A wide range of embedded applications

Features

The features of µC/OS-II include:

• Unprecedented ease-of-use combined with an extremely short learning curve enables rapid time-to-market advantage.
• Runs on the largest number of processor architectures with ports easily downloaded.
• Scalability--Between 5 Kbytes to 24 Kbytes I Max interrupt disable time: 200 clock cycles (typical configuration, ARM9, no wait states).
• Sufficiently robust to meet rigorous safety-critical system requirements
• Complete ANSI C source code is available for a 30-day trial use.

Multi-Threaded Applications

µC/OS-II allows developers to produce multi-threaded applications, vital to the development of safety-critical systems. Thanks to improved integration with IAR Embedded Workbench for ARM, developers can access all the inherent non-reentrant features of C/C++ in a thread-safe manner.

Application developers who write code for use in multi-threaded environments will find the support critical when protecting shared objects using system locks, file-stream locks, and thread-local storage (TLS) in multi-threaded environments.

Micrium and IAR collaborated in providing the first thread-safe support in µC/OS-II for the IAR DLIB run-time library. Protection for such non-reentrant functions as strtok(), rand(), errno() and more are local to each thread. Global and static variables typically used by these functions are protected by the Micrium kernel.

Who should use this RTOS?	Developers who want to save time on their current and next embedded system project, and who want the cleanest, most popular, and robust RTOS on the market.
Supported Processors	See complete list in Processor Chart
Maximum ROM Footprint (Unscaled)	24 Kbytes
Minimum ROM Footprint (Scaled)	6 Kbytes
Number of Kernel Services	10 different using 80 API calls
Multitasking Model	Preemptive
Code Execution Entities	Tasks, ISRs
Dynamic Objects	Static and Dynamic
Data Movement	Message Mailboxes (unlimited)and Message Queues (unlimited)
Semaphores - Full Counting	Yes (unlimited)
Mutexes - With Priority Inheritance	Yes (priority calling)
Event Flags	Yes (unlimited), configurable for 8, 16, or 32 bits
Memory Partitions - RAM Management	Yes
Timers	Yes (unlimited)

Communications Stacks and Middleware

	Requires an RTOS	RTOS not Required
μC/TCP-IP TCP/IP Networking Small RAM/ROM footprint, IP v4	X	-
μC/USB Host USB Host stack	-	X
μC/USB Device USB Device stack	-	X
μC/USB OTG USB Host and Device stack	-	X
μC/FS FAT and FAT-Free File System	-	X
μC/CAN CAN Open Stack	-	X
μC/GUI Graphical User Interface	-	X

The current μC/USB-Host version is V3.10. In version 3.20 it will be available to run without a RTOS

Plug-Ins and Tools

μC/OS-II Kernel Awareness Plug-In (KA) allows for the display of μC/OS-II’s internal data structures in a series of windows integrated with the C-SPY Debugger from IAR’s Embedded Workbench. This allows you to examine each task, semaphore, mutex, mailbox, queue, and event flag group, as well as tasks waiting on kernel objects.

Monitoring

Use μC/Probe to visualize all μC/OS-II -based applications allowing a design engineer to monitor and change values in a product at run time. μC/Probe interfaces to any embedded target whether or not it has a real-time kernel, and works with any (8-bit, 16, bit, 32-bit, 64-bit CPU or DSP. μC/Probe saves valuable time throughout product design, and can also serve as a product’s user interface.

Processor Architectures

Architectures supported by μC/OS-II include:

Company	Architecture
Actel	Cortex-M1
Altera	Nios II, Cortex-M1
Analog Devices	AduC7xxx (ARM7), ADSP-21xx, Blackfin 5xx, SHARC
ARM	ARM7, ARM9, ARM11, Cortex-M1, Cortex-M3
Atmel	SAM7 (ARM7), SAM9(ARM9), AVR, AVR 32
Freescale	9S08, 9S12, Coldfire, PowerPC, i.MX
Fujitsu	FR50
Infineon	TriCore, 80C16x
Intel	80x86
Lattice	Micro32
Luminary Micro	Cortex-M3
Microchip	PIC24, dsPIC33, PIC32 (MIPS)
MIPS	R3000, R4000
NXP	ARM7, ARM9, Cortex-M3
Renesas	H8, M16C, M32C, R32C, RL78, SH, 78Kx, V850
Samsung	ARM7, ARM9
ST	80C16x, STR7 (ARM7), STR9 (ARM9), STM32 (Cortex-M3)
TI	MSP430, TMS320, TMS470, TMS570, Cortex-R4 (ARM7)
Toshiba	Cortex-M3
Xilinx	MicroBlaze, PowerPC
ZILOG	Z80, eZ80

For pricing, delivery, and ordering information, contact Micrium today.